Custom ISA and CPU Datapath Design

I designed and built an 8-bit CPU datapath that can run a binary search algorithm written in assembly. It uses a custom, RISC-5 inspired instruction set, and includes all the usual pieces you need to actually execute a program: an instruction set, a datapath, a control unit, and a memory hierarchy.

The CPU uses a Harvard architecture, so instruction memory and data memory are kept separate. That lets it fetch an instruction and access data at the same time, which keeps the throughput up during execution. I built and verified the whole thing in Intel Quartus Prime.

The instruction set has around 16 opcodes, picked specifically to support binary search. The algorithm keeps a left and right boundary, works out the middle index, and compares the middle value against the target to decide which half of the sorted array to look in next.

The datapath is made up of a few main parts: a program counter that coordinates everything, RAM that's 8 bits wide with 10 addressable locations, a register file with 16 addresses of 8 bits each for temporary storage, an ALU that handles addition, subtraction, and left/right bit shifts (with overflow flags for comparisons), and a control unit that reads each opcode and produces the control signals that drive the rest of the CPU.

The project covers the full cycle, from defining the ISA to building the datapath to running the algorithm on it. The binary search ran correctly in simulation, narrowing the search space comparison by comparison until it landed on the target value in the sorted array.